A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise
نویسندگان
چکیده
منابع مشابه
Design and Analysis of Low Standby Leakage Current and Reduce Ground Bounce Noise of Static CMOS 10T Full Adder
In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...
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Nowadays, the portable multimedia electronic devices, which employ signal-processing modules, require power aware structures more than ever. For the applications associating with human senses, approximate arithmetic circuits can be considered to improve performance and power efficiency. On the other hand, scaling has led to some limitations in performance of nanoscale circuits. According...
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Reduction of leakage Power is the major problem in digital circuits. There are various techniques that are used to reduce the leakage power. Variable Body Biasing technique is discussed in this paper. Variable body biasing technique with sleep insertion technique is one of the efficient technique for designing combinational digital circuits which significantly cuts down the leakage current with...
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ژورنال
عنوان ژورنال: Mathematical Problems in Engineering
سال: 2018
ISSN: 1024-123X,1563-5147
DOI: 10.1155/2018/3501041